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User manual Rev. 3 — 19 December 2013  451 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
19.9.1 Master Transmitter mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver 
(see Figure 93
). Before the master transmitter mode can be entered, I2CON must be 
initialized as follows:
 
The I
2
C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be 
set to logic 1 to enable the I
2
C block. If the AA bit is reset, the I
2
C block will not 
acknowledge its own slave address or the General Call address in the event of another 
device becoming master of the bus. In other words, if AA is reset, the I
2
C interface cannot 
enter a slave mode. STA, STO, and SI must be reset.
The master transmitter mode may now be entered by setting the STA bit. The I
2
C logic will 
now test the I
2
C-bus and generate a START condition as soon as the bus becomes free. 
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status 
code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt 
service routine to enter the appropriate state service routine that loads I2DAT with the 
slave address and the data direction bit (SLA+W). The SI bit in I2CON must then be reset 
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an 
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a 
number of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the 
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1). 
The appropriate action to be taken for each of these status codes is detailed in Table 398
. 
After a repeated START condition (state 0x10). The I
2
C block may switch to the master 
receiver mode by loading I2DAT with SLA+R).
 
Table 396. I2CONSET used to initialize Master Transmitter mode
Bit 7 6 5 4 3 2 1 0
Symbol - I2EN STA STO SI AA - -
Value- 1000x- -