UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 299 of 841
14.1 Basic configuration
The UART0/2/3 peripherals are configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bits PCUART0/2/3.
Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled
(PCUART2/3 = 0).
2. Peripheral clock: In the PCLKSEL0 register (Table 40
), select PCLK_UART0; in the
PCLKSEL1 register (Table 41
), select PCLK_UART2/3.
3. Baud rate: In register U0/2/3LCR (Table 279
), set bit DLAB =1. This enables access
to registers DLL (Table 273
) and DLM (Table 274) for setting the baud rate. Also, if
needed, set the fractional baud rate in the fractional divider register (Table 285
).
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR (Table 278
) to enable
FIFO.
5. Pins: Select UART pins through the PINSEL registers and pin modes through the
PINMODE registers (Section 8.5
).
Remark: UART receive pins should not have pull-down resistors enabled.
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR
(Table 279
). This enables access to U0/2/3IER (Table 275). Interrupts are enabled in
the NVIC using the appropriate Interrupt Set Enable register.
7. DMA: UART0/2/3 transmit and receive functions can operate with the GPDMA
controller (see Table 543
).
14.2 Features
• Data sizes of 5, 6, 7, and 8 bits.
• Parity generation and checking: odd, even mark, space or none.
• One or two stop bits.
• 16 byte Receive and Transmit FIFOs.
• Built-in baud rate generator, including a fractional rate divider for great versatility.
• Supports DMA for both transmit and receive.
• Auto-baud capability
• Break generation and detection.
• Multiprocessor addressing mode.
• IrDA mode to support infrared communication.
• Support for software flow control.
UM10360
Chapter 14: LPC176x/5x UART0/2/3
Rev. 3 — 19 December 2013 User manual
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