NXP Semiconductors LPC1769 - Central Miscellaneous Status Register (CANMSR - 0 X4004 0008); Global Acceptance Filter; Acceptance Filter Modes

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User manual Rev. 3 — 19 December 2013 374 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
16.9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008)
16.10 Global acceptance filter
This block provides lookup for received Identifiers (called Acceptance Filtering in CAN
terminology) for all the CAN Controllers. It includes a 512  32 (2 kB) RAM in which
software maintains one to five tables of Identifiers. This RAM can contain up to 1024
Standard Identifiers or 512 Extended Identifiers, or a mixture of both types.
16.11 Acceptance filter modes
The Acceptance Filter can be put into different modes by setting the according AccOff,
AccBP, and eFCAN bits in the Acceptance Filter Mode Register (Section 16.14.1
“Acceptance Filter Mode Register (AFMR - 0x4003 C000)”). During each mode the
access to the Configuration Register and the ID Look-up table is handled differently.
[1] The whole ID Look-up Table RAM is only word accessible.
[2] During the Operating Mode of the Acceptance Filter the Look-up Table can be accessed only to disable or
enable Messages.
A write access to all section configuration registers is only possible during the Acceptance
Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes.
Table 339. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description
Bit Symbol Description Reset Value
0 E1 When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the
CAN1EWL register (same as ES in CAN1GSR)
0
1 E2 When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the
CAN2EWL register (same as ES in CAN2GSR)
0
7:2 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
8 BS1 When 1, the CAN1 controller is currently involved in bus activities (same as BS in
CAN1GSR).
0
9 BS2 When 1, the CAN2 controller is currently involved in bus activities (same as BS in
CAN2GSR).
0
31:10 - Reserved, the value read from a reserved bit is not defined. NA
Table 340. Acceptance filter modes and access control
Acceptance
filter mode
Bit
AccOff
Bit
AccBP
Acceptance
filter state
ID Look-up
table
RAM
[1]
Acceptanc
e filter
config.
registers
CAN controller
message receive
interrupt
Off Mode 1 0 reset &
halted
r/w access
from CPU
r/w access
from CPU
no messages
accepted
Bypass
Mode
X1reset &
halted
r/w access
from CPU
r/w access
from CPU
all messages
accepted
Operating
Mode and
FullCAN
Mode
0 0 running read-only
from CPU
[2]
access from
Acceptance
filter only
hardware
acceptance filtering