UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 804 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
35.3 Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .8
Table 2. Ordering options for LPC176x/5x parts . . . . . . .8
Table 3. LPC176x/5x memory usage and details. . . . . .13
Table 4. APB0 peripherals and base addresses . . . . . .15
Table 5. APB1 peripherals and base addresses . . . . . .16
Table 6. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 7. Summary of system control registers . . . . . . . .19
Table 8. Reset Source Identification register (RSID -
address 0x400F C180) bit description . . . . . . .22
Table 9. External Interrupt registers . . . . . . . . . . . . . . . .25
Table 10. External Interrupt Flag register (EXTINT - address
0x400F C140) bit description . . . . . . . . . . . . . .26
Table 11. External Interrupt Mode register (EXTMODE -
address 0x400F C148) bit description . . . . . . .27
Table 12. External Interrupt Polarity register (EXTPOLAR -
address 0x400F C14C) bit description . . . . . . .27
Table 13. System Controls and Status register (SCS -
address 0x400F C1A0) bit description . . . . . . .29
Table 14. Summary of system control registers . . . . . . . .31
Table 15. Recommended values for C
X1/X2
in oscillation
mode (crystal and external components
parameters) low frequency mode (OSCRANGE =
0, see Table 13
) . . . . . . . . . . . . . . . . . . . . . . . .33
Table 16. Recommended values for C
X1/X2
in oscillation
mode (crystal and external components
parameters) high frequency mode (OSCRANGE =
1, see Table 13
) . . . . . . . . . . . . . . . . . . . . . . . .33
Table 17. Clock Source Select register (CLKSRCSEL -
address 0x400F C10C) bit description . . . . . . .35
Table 18. PLL0 registers . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 19. PLL Control register (PLL0CON - address
0x400F C080) bit description . . . . . . . . . . . . . .38
Table 20. PLL0 Configuration register (PLL0CFG - address
0x400F C084) bit description . . . . . . . . . . . . . .38
Table 21. Multiplier values for PLL0 with a 32 kHz input .39
Table 22. PLL Status register (PLL0STAT - address
0x400F C088) bit description . . . . . . . . . . . . . .40
Table 23. PLL control bit combinations . . . . . . . . . . . . . .41
Table 24. PLL Feed register (PLL0FEED - address
0x400F C08C) bit description. . . . . . . . . . . . . .41
Table 25. PLL frequency parameter. . . . . . . . . . . . . . . . .42
Table 26. Additional Multiplier Values for use with a Low
Frequency Clock Input . . . . . . . . . . . . . . . . . . .43
Table 27. Summary of PLL0 examples . . . . . . . . . . . . . .44
Table 28. Potential values for PLL example. . . . . . . . . . .46
Table 29. PLL1 registers . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 30. PLL1 Control register (PLL1CON - address
0x400F C0A0) bit description . . . . . . . . . . . . . .50
Table 31. PLL Configuration register (PLL1CFG - address
0x400F C0A4) bit description . . . . . . . . . . . . . .50
Table 32. PLL1 Status register (PLL1STAT - address
0x400F C0A8) bit description . . . . . . . . . . . . . .51
Table 33. PLL1 control bit combinations . . . . . . . . . . . . .51
Table 34. PLL1 Feed register (PLL1FEED - address
0x400F C0AC) bit description. . . . . . . . . . . . . .52
Table 35. Elements determining PLL frequency. . . . . . . .53
Table 36. PLL1 Divider values . . . . . . . . . . . . . . . . . . . . 54
Table 37. PLL1 Multiplier values . . . . . . . . . . . . . . . . . . . 54
Table 38. CPU Clock Configuration register (CCLKCFG -
address 0x400F C104) bit description . . . . . . . 56
Table 39. USB Clock Configuration register (USBCLKCFG -
address 0x400F C108) bit description . . . . . . . 57
Table 40. Peripheral Clock Selection register 0 (PCLKSEL0
- address 0x400F C1A8) bit description. . . . . . 57
Table 41. Peripheral Clock Selection register 1 (PCLKSEL1
- address 0x400F C1AC) bit description . . . . . 58
Table 42. Peripheral Clock Selection register bit values . 58
Table 43. Power Control registers . . . . . . . . . . . . . . . . . . 61
Table 44. Power Mode Control register (PCON - address
0x400F C0C0) bit description . . . . . . . . . . . . . 62
Table 45. Encoding of reduced power modes . . . . . . . . . 63
Table 46. Power Control for Peripherals register (PCONP -
address 0x400F C0C4) bit description. . . . . . . 64
Table 47. Clock Output Configuration register
(CLKOUTCFG - 0x400F C1C8) bit description 67
Table 48. Summary of flash accelerator registers . . . . . . 70
Table 49. Flash Accelerator Configuration register
(FLASHCFG - address 0x400F C000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 50. Connection of interrupt sources to the Vectored
Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . 74
Table 51. NVIC register map . . . . . . . . . . . . . . . . . . . . . 77
Table 52. Interrupt Set-Enable Register 0 register (ISER0 -
0xE000 E100) . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 53. Interrupt Set-Enable Register 1 register (ISER1 -
0xE000 E104) . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 54. Interrupt Clear-Enable Register 0 (ICER0 -
0xE000 E180) . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 55. Interrupt Clear-Enable Register 1 register (ICER1
- 0xE000 E184) . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 56. Interrupt Set-Pending Register 0 register (ISPR0 -
0xE000 E200) . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 57. Interrupt Set-Pending Register 1 register (ISPR1 -
0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 58. Interrupt Clear-Pending Register 0 register
(ICPR0 - 0xE000 E280) . . . . . . . . . . . . . . . . . 84
Table 59. Interrupt Set-Pending Register 1 register (ISPR1 -
0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 60. Interrupt Active Bit Register 0 (IABR0 - 0xE000
E300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 61. Interrupt Active Bit Register 1 (IABR1 - 0xE000
E304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000
E400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000
E404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000
E408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000
E40C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000
E410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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