UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 805 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000
E414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000
E418) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000
E41C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 70. Interrupt Priority Register 8 (IPR8 - 0xE000
E420) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 71. Software Trigger Interrupt Register (STIR -
0xE000 EF00) . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 72. Pin allocation table TFBGA100 package . . . . .93
Table 73. Pin description . . . . . . . . . . . . . . . . . . . . . . . . .96
Table 74. Summary of PINSEL registers . . . . . . . . . . . .105
Table 75. Pin function select register bits. . . . . . . . . . . .106
Table 76. Pin Mode Select register Bits . . . . . . . . . . . . .106
Table 77. Open Drain Pin Mode Select register Bits . . .107
Table 78. Pin Connect Block Register Map . . . . . . . . . .108
Table 79. Pin function select register 0 (PINSEL0 - address
0x4002 C000) bit description . . . . . . . . . . . . .109
Table 80. Pin function select register 1 (PINSEL1 - address
0x4002 C004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 81. Pin function select register 2 (PINSEL2 - address
0x4002 C008) bit description . . . . . . . . . . . . .110
Table 82. Pin function select register 3 (PINSEL3 - address
0x4002 C00C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 83. Pin function select register 4 (PINSEL4 - address
0x4002 C010) bit description . . . . . . . . . . . . . 111
Table 84. Pin function select register 7 (PINSEL7 - address
0x4002 C01C) bit description . . . . . . . . . . . .112
Table 85. Pin function select register 9 (PINSEL9 - address
0x4002 C024) bit description . . . . . . . . . . . . .112
Table 86. Pin function select register 10 (PINSEL10 -
address 0x4002 C028) bit description . . . . . .112
Table 87. Pin Mode select register 0 (PINMODE0 - address
0x4002 C040) bit description . . . . . . . . . . . . .113
Table 88. Pin Mode select register 1 (PINMODE1 - address
0x4002 C044) bit description . . . . . . . . . . . . .113
Table 89. Pin Mode select register 2 (PINMODE2 - address
0x4002 C048) bit description . . . . . . . . . . . . .114
Table 90. Pin Mode select register 3 (PINMODE3 - address
0x4002 C04C) bit description . . . . . . . . . . . . .114
Table 91. Pin Mode select register 4 (PINMODE4 - address
0x4002 C050) bit description . . . . . . . . . . . . .115
Table 92. Pin Mode select register 7 (PINMODE7 - address
0x4002 C05C) bit description . . . . . . . . . . . . .116
Table 93. Pin Mode select register 9 (PINMODE9 - address
0x4002 C064) bit description . . . . . . . . . . . . .116
Table 94. Open Drain Pin Mode select register 0
(PINMODE_OD0 - address 0x4002 C068) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 95. Open Drain Pin Mode select register 1
(PINMODE_OD1 - address 0x4002 C06C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 96. Open Drain Pin Mode select register 2
(PINMODE_OD2 - address 0x4002 C070) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 97. Open Drain Pin Mode select register 3
(PINMODE_OD3 - address 0x4002 C074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 98. Open Drain Pin Mode select register 4
(PINMODE_OD4 - address 0x4002 C078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 99. I2C Pin Configuration register (I2CPADCFG -
address 0x4002 C07C) bit description. . . . . . 120
Table 100. GPIO pin description. . . . . . . . . . . . . . . . . . . 122
Table 101. GPIO register map (local bus accessible registers
- enhanced GPIO features) . . . . . . . . . . . . . . 123
Table 102. GPIO interrupt register map . . . . . . . . . . . . . 124
Table 103. Fast GPIO port Direction register FIO0DIR to
FIO4DIR - addresses 0x2009 C000 to 0x2009
C080) bit description . . . . . . . . . . . . . . . . . . . 124
Table 104. Fast GPIO port Direction control byte and
half-word accessible register description. . . . 125
Table 105. Fast GPIO port output Set register (FIO0SET to
FIO4SET - addresses 0x2009 C018 to 0x2009
C098) bit description . . . . . . . . . . . . . . . . . . . 126
Table 106. Fast GPIO port output Set byte and half-word
accessible register description. . . . . . . . . . . . 126
Table 107. Fast GPIO port output Clear register (FIO0CLR to
FIO4CLR- addresses 0x2009 C01C to 0x2009
C09C) bit description . . . . . . . . . . . . . . . . . . . 127
Table 108. Fast GPIO port output Clear byte and half-word
accessible register
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 109. Fast GPIO port Pin value register (FIO0PIN to
FIO4PIN- addresses 0x2009 C014 to 0x2009
C094) bit description . . . . . . . . . . . . . . . . . . . 129
Table 110. Fast GPIO port Pin value byte and half-word
accessible register
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 111. Fast GPIO port Mask register (FIO0MASK to
FIO4MASK - addresses 0x2009 C010 to 0x2009
C090) bit description . . . . . . . . . . . . . . . . . . . 130
Table 112. Fast GPIO port Mask byte and half-word
accessible register description. . . . . . . . . . . . 131
Table 113. GPIO overall Interrupt Status register (IOIntStatus
- address 0x4002 8080) bit description . . . . . 132
Table 114. GPIO Interrupt Enable for port 0 Rising Edge
(IO0IntEnR - 0x4002 8090) bit description . . 132
Table 115. GPIO Interrupt Enable for port 2 Rising Edge
(IO2IntEnR - 0x4002 80B0) bit description . . 133
Table 116. GPIO Interrupt Enable for port 0 Falling Edge
(IO0IntEnF - address 0x4002 8094) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
T
a
ble 117. GPIO Interrupt Enable for port 2 Falling Edge
(IO2IntEnF - 0x4002 80B4) bit description. . . 135
Table 118. GPIO Interrupt Status for port 0 Rising Edge
Interrupt (IO0IntStatR - 0x4002 8084) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 119. GPIO Interrupt Status for port 2 Rising Edge
Interrupt (IO2IntStatR - 0x4002 80A4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 120. GPIO Interrupt Status for port 0 Falling Edge
Interrupt (IO0IntStatF - 0x4002 8088) bit
To Next Page
Loading...
