UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 806 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
description . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Table 121. GPIO Interrupt Status for port 2 Falling Edge
Interrupt (IO2IntStatF - 0x4002 80A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr
- 0x4002 808C)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Table 123. GPIO Interrupt Clear register for port 2 (IO2IntClr
- 0x4002 80AC) bit description . . . . . . . . . . . .140
Table 124. Ethernet acronyms, abbreviations, and
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Table 125. Example PHY Devices. . . . . . . . . . . . . . . . . .148
Table 126. Ethernet RMII pin descriptions. . . . . . . . . . . .148
Table 127. Ethernet MIIM pin descriptions . . . . . . . . . . .148
Table 128. Ethernet register definitions . . . . . . . . . . . . .149
Table 129. MAC Configuration register 1 (MAC1 - address
0x5000 0000) bit description . . . . . . . . . . . . .151
Table 130. MAC Configuration register 2 (MAC2 - address
0x5000 0004) bit description . . . . . . . . . . . . .152
Table 131. Pad operation . . . . . . . . . . . . . . . . . . . . . . . .153
Table 132. Back-to-back Inter-packet-gap register (IPGT -
address 0x5000 0008) bit description. . . . . . .153
Table 133. Non Back-to-back Inter-packet-gap register
(IPGR - address 0x5000 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Table 134. Collision Window / Retry register (CLRT - address
0x5000 0010) bit description . . . . . . . . . . . . .154
Table 135. Maximum Frame register (MAXF - address
0x5000 0014) bit description . . . . . . . . . . . . .154
Table 136. PHY Support register (SUPP - address
0x5000 0018) bit description . . . . . . . . . . . . .154
Table 137. Test register (TEST - address 0x5000 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Table 138. MII Mgmt Configuration register (MCFG - address
0x5000 0020) bit description . . . . . . . . . . . . .155
Table 139. Clock select encoding. . . . . . . . . . . . . . . . . .155
Table 140. MII Mgmt Command register (MCMD - address
0x5000 0024) bit description . . . . . . . . . . . . .156
Table 141. MII Mgmt Address register (MADR - address
0x5000 0028) bit description . . . . . . . . . . . . .156
Table 142. MII Mgmt Write Data register (MWTD - address
0x5000 002C) bit description . . . . . . . . . . . . .157
Table 143. MII Mgmt Read Data register (MRDD - address
0x5000 0030) bit description . . . . . . . . . . . . .157
Table 144. MII Mgmt Indicators register (MIND - address
0x5000 0034) bit description . . . . . . . . . . . . .157
Table 145. Station Address register (SA0 - address
0x5000 0040) bit description . . . . . . . . . . . . .158
Table 146. Station Address register (SA1 - address
0x5000 0044) bit description . . . . . . . . . . . . .158
Table 147. Station Address register (SA2 - address
0x5000 0048) bit description . . . . . . . . . . . . .158
Table 148. Command register (Command - address
0x5000 0100) bit description . . . . . . . . . . . . .159
Table 149. Status register (Status - address 0x5000 0104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Table 150. Receive Descriptor Base Address register
(RxDescriptor - address 0x5000 0108) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 151. receive Status Base Address register (RxStatus -
address 0x5000 010C) bit description . . . . . . 160
Table 152. Receive Number of Descriptors register
(RxDescriptor - address 0x5000 0110) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 153. Receive Produce Index register
(RxProduceIndex - address 0x5000 0114) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 154. Receive Consume Index register
(RxConsumeIndex - address 0x5000 0118) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 155. Transmit Descriptor Base Address register
(TxDescriptor - address 0x5000 011C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 156. Transmit Status Base Address register (TxStatus
- address 0x5000 0120) bit description . . . . . 162
Table 157. Transmit Number of Descriptors register
(TxDescriptorNumber - address 0x5000 0124) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 158. Transmit Produce Index register
(TxProduceIndex - address 0x5000 0128) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 159. Transmit Consume Index register
(TxConsumeIndex - address 0x5000 012C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 160. Transmit Status Vector 0 register (TSV0 -
address 0x5000 0158) bit description . . . . . . 164
Table 161. Transmit Status Vector 1 register (TSV1 - address
0x5000 015C) bit description . . . . . . . . . . . . . 165
Table 162. Receive Status Vector register (RSV - address
0x5000 0160) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 163. Flow Control Counter register
(FlowControlCounter - address 0x5000 0170) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 164. Flow Control Status register (FlowControlStatus -
address 0x5000 0174) bit description . . . . . . 166
Table 165. Receive Filter Control register (RxFilterCtrl -
address 0x5000 0200) bit description . . . . . . 167
Table 166. Receive Filter WoL Status register
(RxFilterWoLStatus - address 0x5000 0204) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 167. Receive Filter WoL Clear register
(RxFilterWoLClear - address 0x5000 0208) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 168. Hash Filter Table LSBs register (HashFilterL -
address 0x5000 0210) bit description . . . . . . 168
T
ab
le 169. Hash Filter MSBs register (HashFilterH - address
0x5000 0214) bit description . . . . . . . . . . . . . 169
Table 170. Interrupt Status register (IntStatus - address
0x5000 0FE0) bit description . . . . . . . . . . . . . 169
Table 171. Interrupt Enable register (intEnable - address
0x5000 0FE4) bit description . . . . . . . . . . . . . 170
Table 172. Interrupt Clear register (IntClear - address
0x5000 0FE8) bit description . . . . . . . . . . . . . 171
Table 173. Interrupt Set register (IntSet - address
0x5000 0FEC) bit description. . . . . . . . . . . . . 171
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