UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 59 of 841
NXP Semiconductors
UM10360
Chapter 4: LPC176x/5x Clocking and power control
4.8 Power control
The LPC176x/5x supports a variety of power control features: Sleep mode, Deep Sleep
mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be
controlled as needed by changing clock sources, re-configuring PLL values, and/or
altering the CPU clock divider value. This allows a trade-off of power versus processing
speed based on application requirements. In addition, Peripheral Power Control allows
shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application.
Entry to any reduced power mode begins with the execution of either a WFI (Wait For
Interrupt) or WFE (Wait For Exception) instruction by the Cortex-M3. The Cortex-M3
internally supports two reduced power modes: Sleep and Deep Sleep. These are selected
by the SLEEPDEEP bit in the cortex-M3 System Control Register. Power-down and Deep
Power-down modes are selected by bits in the PCON register. See Table 44
. The same
register contains flags that indicate whether entry into each reduced power mode actually
occurred.
The LPC176x/5x also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the Real Time Clock.
Reduced power modes have some limitation during debug, see Section 33.5
for more
information.
4.8.1 Sleep mode
Note: Sleep mode on the LPC176x/5x corresponds to the Idle mode on LPC2xxx series
devices. The name is changed because ARM has incorporated portions of reduced power
mode control into the Cortex-M3. LPC176x/5x documentation uses the Cortex-M3
terminology where applicable.
When Sleep mode is entered, the clock to the core is stopped, and the SMFLAG bit in
PCON is set, see Table 44
.Resumption from the Sleep mode does not need any special
sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a Reset or an interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
The GPDMA may operate in Sleep mode to access AHB SRAMs and peripherals with
GPDMA support, but the GPDMA cannot access the flash memory or the main SRAM,
which are disabled in order to save power.
Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.
4.8.2 Deep Sleep mode
Note: Deep Sleep mode on the LPC176x/5x corresponds to the Sleep mode on LPC23xx
and LPC24xx series devices. The name is changed because ARM has incorporated
portions of reduced power mode control into the Cortex-M3. LPC176x/5x documentation
uses the Cortex-M3 terminology where applicable.
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