UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 88 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400)
The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.5.12 Interrupt Priority Register 1 (IPR1 - 0xE000 E404)
The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
6.5.13 Interrupt Priority Register 2 (IPR2 - 0xE000 E408)
The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000 E400)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_WDT Watchdog Timer Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_TIMER0 Timer 0 Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_TIMER1 Timer 1 Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_TIMER2 Timer 2 Interrupt Priority. See functional description for bits 7-3.
Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000 E404)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_TIMER3 Timer 3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_UART0 UART0 Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_UART1 UART1 Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_UART2 UART2 Interrupt Priority. See functional description for bits 7-3.
Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000 E408)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_UART3 UART3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_PWM PWM Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_I2C0 I
2
C0 Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_I2C1 I
2
C1 Interrupt Priority. See functional description for bits 7-3.
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