UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 331 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
15.4.11 UART1 Modem Status Register (U1MSR - 0x4001 0018)
The U1MSR is a read-only register that provides status information on the modem input
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
effect on UART1 operation, they facilitate software implementation of modem signal
operations.
3 Framing Error
(FE)
When the stop bit of a received character is a logic 0, a framing error occurs. An
U1LSR read clears U1LSR[3]. The time of the framing error detection is
dependent on U1FCR0. Upon detection of a framing error, the RX will attempt to
resynchronize to the data and assume that the bad stop bit is actually an early
start bit. However, it cannot be assumed that the next received byte will be correct
even if there is no Framing Error.
Note: A framing error is associated with the character at the top of the UART1
RBR FIFO.
0
0 Framing error status is inactive.
1 Framing error status is active.
4 Break Interrupt
(BI)
When RXD1 is held in the spacing state (all zeroes) for one full character
transmission (start, data, parity, stop), a break interrupt occurs. Once the break
condition has been detected, the receiver goes idle until RXD1 goes to marking
state (all ones). An U1LSR read clears this status bit. The time of break detection
is dependent on U1FCR[0].
Note: The break interrupt is associated with the character at the top of the UART1
RBR FIFO.
0
0 Break interrupt status is inactive.
1 Break interrupt status is active.
5 Transmitter
Holding Register
Empty (THRE)
THRE is set immediately upon detection of an empty UART1 THR and is cleared
on a U1THR write.
1
0 U1THR contains valid data.
1 U1THR is empty.
6 Transmitter
Empty (TEMT)
TEMT is set when both U1THR and U1TSR are empty; TEMT is cleared when
either the U1TSR or the U1THR contain valid data.
1
0 U1THR and/or the U1TSR contains valid data.
1 U1THR and the U1TSR are empty.
7 Error in RX FIFO
(RXFE)
U1LSR[7] is set when a character with a RX error such as framing error, parity
error or break interrupt, is loaded into the U1RBR. This bit is cleared when the
U1LSR register is read and there are no subsequent errors in the UART1 FIFO.
0
0 U1RBR contains no UART1 RX errors or U1FCR[0]=0.
1 UART1 RBR contains at least one UART1 RX error.
31:8 - Reserved, the value read from a reserved bit is not defined. NA
Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description …continued
Bit Symbol Value Description Reset
Value
Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description
Bit Symbol Value Description Reset Value
0 Delta CTS Set upon state change of input CTS. Cleared on an U1MSR read. 0
0 No change detected on modem input, CTS.
1 State change detected on modem input, CTS.
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