UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 91 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00)
The STIR register provides an alternate way for software to generate an interrupt, in
addition to using the ISPR registers. This mechanism can only be used to generate
peripheral interrupts, not system exceptions.
By default, only privileged software can write to the STIR register. Unprivileged software
can be given this ability if privileged software sets the USERSETMPEND bit in the CCR
register (see Section 34.4.3.8
).
Table 71. Software Trigger Interrupt Register (STIR - 0xE000 EF00)
Bit Name Function
8:0 INTID Writing a value to this field generates an interrupt for the specified the interrupt number (see
Table 50
). The range allowed for the LPC176x/5x is 0 to 111.
31:9 - Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
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