UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 45 of 841
NXP Semiconductors
UM10360
Chapter 4: LPC176x/5x Clocking and power control
Example 2
Assumptions:
• The USB interface will be used in the application and will be clocked from PLL0.
• The desired CPU rate is 60 MHz.
• An external 4 MHz crystal or clock source will be used as the system clock source.
This clock source could be the Internal RC oscillator (IRC).
Calculations:
M = (F
CCO
N) / (2 F
IN
)
Because supporting USB requires a precise 48 MHz clock with a 50% duty cycle, that
need must be addressed first. Potential precise values of F
CCO
are integer multiples of the
2 the 48 MHz USB clock. The 2 insures that the clock has a 50% duty cycle, which
would not be the case for a division of the PLL output by an odd number.
The possibilities for the F
CCO
rate when the USB is used are 288 MHz, 384 MHz, and 480
MHz. The smallest frequency for F
CCO
that can produce a valid USB clock rate and is
within the PLL0 operating range is 288 MHz (3 2 48 MHz).
Start by assuming N = 1, since this produces the smallest multiplier needed for PLL0. So,
M = ((288 10
6
) 1) / (2 (4 10
6)
) = 288 / 8 = 36. The result is an integer, which is
necessary to obtain a precise USB clock. The value written to PLL0CFG would be 0x23
(N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing F
CCO
by the desired CPU
frequency: 288 10
6
/60 10
6
= 4.8. The nearest integer value for the CPU Clock
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an F
CCO
rate must be found that can be divided
down to both 48 MHz and 60 MHz. As previously noted, the possibilities for the F
CCO
rate
when the USB is used are 288 MHz, 384 MHz, and 480 MHz. Of these, only is 480 MHz is
also evenly divisible by 60. Divided by 10, this gives the 48 MHz with a 50% duty cycle
needed by the USB subsystem. Divided by 8, it gives 60 MHz for the CPU clock. PLL0
settings for 480 MHz are N = 1 and M = 60.
The PLL output must be further divided in order to produce both the CPU clock and the
USB clock. This is accomplished using separate dividers that are described later in this
chapter. See Section 4.7.1
and Section 4.7.2.
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