UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 534 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028,
0x400B 802C)
These registers hold the limiting values for timer/counters 0-2. When a timer/counter
reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts
over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which
time it begins counting up again.
If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, the match
between TC and LIM switches the channel’s A output from “active” to “passive” state. If
the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously
switches the channel’s B output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B
output switches from “passive” to “active” state.
In center-aligned mode, matches between a channel’s TC and LIM registers have no
effect on its A and B outputs.
25.7.6.1 Match and Limit write and operating registers
Writing to either a Limit or a Match register loads a “write” register, and, if the channel is
stopped, it also loads a shadow “operating” register that is compared to the TC. If the
channel is running and its “disable update” bit in MCCON is 0, the operating registers are
loaded from the write registers as follows:
1. in edge-aligned mode, when the TC matches the operating Limit register;
2. in center-aligned mode, when the TC counts back down to 0. If the channel is running
and the “disable update” bit is 1, the operating registers are not loaded from the write
registers until software stops the channel.
Reading an MCLIM register address always returns the operating value.
Simultaneous update of the Limit and Match registers can be achieved by writing the
MCLIMx and MCMATx registers and then clearing the DISUPx bits in the MCCON register
(see Table 457
). The simultaneous update will occur at the beginning of the next PWM
cycle (also see Section 25.8.2
).
Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined
by its Limit register, and the pulse width at the start of the period is determined by its
Match register. You can consider the Limit register to be a “Period register” and the Match
register to be a “Pulse Width register”.
Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description
Bit Symbol Description Reset value
31:0 MCTC0/1/2 Timer/Counter values for channels 0, 1, 2. 0
Table 473. MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) bit description
Bit Symbol Description Reset value
31:0 MCLIM0/1/2 Limit values for TC0, 1, 2. 0xFFFF FFFF
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