UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 765 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
See Table 645 for more information about the
IP[0]
to
IP[111]
interrupt priority array, that
provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt N as follows:
• the corresponding IPR number, M, is given by M = N DIV 4
• the byte offset of the required Priority field in this register is N MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
34.4.2.8 Software Trigger Interrupt Register
Write to the STIR to generate a Software Generated Interrupt (SGI). See the register
summary in Table 644
for the STIR attributes.
When the USERSETMPEND bit in the CCR is set to 1, unprivileged software can access
the STIR, see Section 34.4.3.8 “
Configuration and Control Register”.
Remark: Only privileged software can enable unprivileged access to the STIR.
The bit assignments are shown in Table 652
.
34.4.2.9 Level-sensitive and pulse interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the
peripheral must assert the interrupt signal for at least one clock cycle, during which the
NVIC detects the pulse and latches the interrupt.
Table 651. IPR bit assignments
Bits Name Function
[31:24] Priority, byte offset 3 Each priority field holds a priority value, 0-31. The lower the
value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:3] of each field, bits[2:0]
read as zero and ignore writes.
[23:16] Priority, byte offset 2
[15:8] Priority, byte offset 1
[7:0] Priority, byte offset 0
Table 652. STIR bit assignments
Bits Field Function
[31:9] - Reserved.
[8:0] INTID Interrupt ID of the required SGI, in the range 0-111. For example, a value
of b000000011 specifies interrupt IRQ3.
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