UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 684 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate
Right with Extend.
34.2.5.3.1 Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
ASR:
Arithmetic Shift Right.
LSL:
Logical Shift Left.
LSR
: Logical Shift Right.
ROR:
Rotate Right.
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7 “
Conditional execution”.
Rd is the destination register.
Rm is the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
Rs s the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shift length depends on the instruction:
ASR:
shift length from 1 to 32
LSL:
shift length from 0 to 31
LSR:
shift length from 1 to 32
ROR:
shift length from 1 to 31
Remark:
MOV{S}{cond} Rd, Rm
is the preferred syntax for
LSL{S}{cond} Rd, Rm, #0
.
34.2.5.3.2 Operation
ASR
,
LSL
,
LSR
, and
ROR
move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
RRX
moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see
Section 34.2.3.4 “
Shift Operations”.
34.2.5.3.3 Restrictions
Do not use SP and do not use PC.
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