NXP Semiconductors LPC1769 - UART1 Line Status Register (U1 LSR - 0 X4001 0014)

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 330 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
data present in the transmit FIFO and a receiver overrun error can result. Figure 49
illustrates the Auto-CTS functional timing.
While starting transmission of the initial character the CTS1 signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets
de-asserted transmission resumes and a start bit is sent followed by the data bits of the
next character.
15.4.10 UART1 Line Status Register (U1LSR - 0x4001 0014)
The U1LSR is a read-only register that provides status information on the UART1 TX and
RX blocks.
Fig 49. Auto-CTS Functional Timing
start bits0..7 start bits0..7 stop start bits0..7 stop
UART1 TX
CTS1 pin
~ ~
~ ~
~ ~
~ ~
stop
Table 301: UART1 Line Status Register (U1LSR - address 0x4001 0014) bit description
Bit Symbol Value Description Reset
Value
0 Receiver Data
Ready (RDR)
U1LSR[0] is set when the U1RBR holds an unread character and is cleared when
the UART1 RBR FIFO is empty.
0
0 The UART1 receiver FIFO is empty.
1 The UART1 receiver FIFO is not empty.
1 Overrun Error
(OE)
The overrun error condition is set as soon as it occurs. An U1LSR read clears
U1LSR[1]. U1LSR[1] is set when UART1 RSR has a new character assembled
and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be
overwritten and the character in the UART1 RSR will be lost.
0
0 Overrun error status is inactive.
1 Overrun error status is active.
2 Parity Error (PE) When the parity bit of a received character is in the wrong state, a parity error
occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is
dependent on U1FCR[0].
Note: A parity error is associated with the character at the top of the UART1 RBR
FIFO.
0
0 Parity error status is inactive.
1 Parity error status is active.