UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 81 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184)
The ICER1 register allows disabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Enabling interrupts is done through the
ISER0 and ISER1 registers (Section 6.5.1
and Section 6.5.2).
Table 55. Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184)
Bit Name Function
0 ICE_PLL1 PLL1 (USB PLL) Interrupt Disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
1 ICE_USBACT USB Activity Interrupt Disable. See functional description for bit 0.
2 ICE_CANACT CAN Activity Interrupt Disable. See functional description for bit 0.
31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit
is not defined.
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