UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 321 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
15.4 Register description
UART1 contains registers organized as shown in Table 289. The Divisor Latch Access Bit
(DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 289: UART1 register map
Name Description Access Reset
Value
[1]
Address
U1RBR
(when DLAB =0)
Receiver Buffer Register. Contains the next received character to
be read.
RO NA 0x4001 0000
(when DLAB=0)
U1THR
(when DLAB =0)
Transmit Holding Register. The next character to be transmitted is
written here.
WO NA 0x4001 0000
(when DLAB=0)
U1DLL
(when DLAB =1)
Divisor Latch LSB. Least significant byte of the baud rate divisor
value. The full divisor is used to generate a baud rate from the
fractional rate divider.
R/W 0x01 0x4001 0000
(when DLAB=1)
U1DLM
(when DLAB =1)
Divisor Latch MSB. Most significant byte of the baud rate divisor
value. The full divisor is used to generate a baud rate from the
fractional rate divider.
R/W 0x00 0x4001 0004
(when DLAB=1)
U1IER
(when DLAB =0)
Interrupt Enable Register. Contains individual interrupt enable bits
for the 7 potential UART1 interrupts.
R/W 0x00 0x4001 0004
(when DLAB=0)
U1IIR Interrupt ID Register. Identifies which interrupt(s) are pending. RO 0x01 0x4001 0008
U1FCR FIFO Control Register. Controls UART1 FIFO usage and modes. WO 0x00 0x4001 0008
U1LCR Line Control Register. Contains controls for frame formatting and
break generation.
R/W 0x00 0x4001 000C
U1MCR Modem Control Register. Contains controls for flow control
handshaking and loopback mode.
R/W 0x00 0x4001 0010
U1LSR Line Status Register. Contains flags for transmit and receive status,
including line errors.
RO 0x60 0x4001 0014
U1MSR Modem Status Register. Contains handshake signal status flags. RO 0x00 0x4001 0018
U1SCR Scratch Pad Register. 8-bit temporary storage for software. R/W 0x00 0x4001 001C
U1ACR Auto-baud Control Register. Contains controls for the auto-baud
feature.
R/W 0x00 0x4001 0020
U1FDR Fractional Divider Register. Generates a clock input for the baud
rate divider.
R/W 0x10 0x4001 0028
U1TER Transmit Enable Register. Turns off UART transmitter for use with
software flow control.
R/W 0x80 0x4001 0030
U1RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various
aspects of RS-485/EIA-485 modes.
R/W 0x00 0x4001 004C
U1ADRMATCH RS-485/EIA-485 address match. Contains the address match value
for RS-485/EIA-485 mode.
R/W 0x00 0x4001 0050
U1RS485DLY RS-485/EIA-485 direction control delay. R/W 0x00 0x4001 0054
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