NXP Semiconductors LPC1769 - Transmit Clock Bit Rate Register (I2 STXBITRATE - 0 X400 A 8028); Receive Clock Bit Rate Register (I2 SRXBITRATE - 0 X400 A 802 C); Transmit Mode Control Register (I2 STXMODE - 0 X400 A 8030)

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 482 of 841
NXP Semiconductors
UM10360
Chapter 20: LPC176x/5x I2S
20.5.11 Transmit Clock Bit Rate register (I2STXBITRATE - 0x400A 8028)
The bit rate for the I
2
S transmitter is determined by the value of the I2STXBITRATE
register. The value depends on the audio sample rate desired, and the data size and
format (stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data
requires a bit rate of 48,000162 = 1.536 MHz.
20.5.12 Receive Clock Bit Rate register (I2SRXBITRATE - 0x400A 802C)
The bit rate for the I
2
S receiver is determined by the value of the I2SRXBITRATE register.
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for I2SRXBITRATE.
20.5.13 Transmit Mode Control register (I2STXMODE - 0x400A 8030)
The Transmit Mode Control register contains additional controls for transmit clock source,
enabling the 4-pin mode, and how MCLK is used. See Section 20.7
for a summary of
useful mode combinations.
Table 414: Receive Clock Rate register (I2SRXRATE - address 0x400A 8024) bit description
Bit Symbol Description Reset
Value
7:0 Y_divider I
2
S receive MCLK rate denominator. This value is used to divide PCLK to produce the
receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of
0 stops the clock.
0
15:8 X_divider
I
2
S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the
receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide
range of possibilities. Note: the resulting ratio X/Y is divided by 2.
0
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 415: Transmit Clock Rate register (I2TXBITRATE - address 0x400A 8028) bit description
Bit Symbol Description Reset
Value
5:0 tx_bitrate I
2
S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit
clock.
0
31:6 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 416: Receive Clock Rate register (I2SRXBITRATE - address 0x400A 802C) bit description
Bit Symbol Description Reset
Value
5:0 rx_bitrate I
2
S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit
clock.
0
31:6 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA