UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 782 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.4.3.12 Hard Fault Status Register
The HFSR gives information about events that activate the hard fault handler. See the
register summary in Table 654
for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but
writing 1 to any bit clears that bit to 0. The bit assignments are shown in Table 671
.
Remark: The HFSR bits are sticky. This means as one or more fault occurs, the
associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit,
or by a reset.
34.4.3.13 Memory Management Fault Address Register
The MMFAR contains the address of the location that generated a memory management
fault. See the register summary in Table 654
for its attributes. The bit assignments are:
When an unaligned access faults, the address is the actual address that faulted. Because
a single read or write instruction can be split into multiple aligned accesses, the fault
address can be any address in the range of the requested access size.
Flags in the MMFSR indicate the cause of the fault, and whether the value in the MMFAR
is valid. See Table 668
.
34.4.3.14 Bus Fault Address Register
The BFAR contains the address of the location that generated a bus fault. See the register
summary in Table 654
for its attributes. The bit assignments are:
Table 671. HFSR bit assignments
Bits Name Function
[31] DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to
this bit, otherwise behavior is Unpredictable.
[30] FORCED Indicates a forced hard fault, generated by escalation of a fault with
configurable priority that cannot be handles, either because of priority or
because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault
status registers to find the cause of the fault.
[29:2] - Reserved.
[1] VECTTBL Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return
points to the instruction that was preempted by the exception.
[0] - Reserved.
Table 672. MMFAR bit assignments
Bits Name Function
[31:0] ADDRESS When the MMARVALID bit of the MMFSR is set to 1, this field holds the
address of the location that generated the memory management fault
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