UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 597 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.5.5 DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)
The DMACIntErrClr Register is write-only and clears the error interrupt requests. When
writing to this register, each data bit that is 1 causes the corresponding bit in the status
register to be cleared. Data bits that are 0 have no effect on the corresponding bit in the
register. Table 549
shows the bit assignments of the DMACIntErrClr Register.
31.5.6 DMA Raw Interrupt Terminal Count Status register
(DMACRawIntTCStat - 0x5000 4014)
The DMACRawIntTCStat Register is read-only and indicates which DMA channel is
requesting a transfer complete (terminal count interrupt) prior to masking. (Note: the
DMACIntTCStat Register contains the same information after masking.) A 1 bit indicates
that the terminal count interrupt request is active prior to masking. Table 550
shows the bit
assignments of the DMACRawIntTCStat Register.
31.5.7 DMA Raw Error Interrupt Status register (DMACRawIntErrStat -
0x5000 4018)
The DMACRawIntErrStat Register is read-only and indicates which DMA channel is
requesting an error interrupt prior to masking. (Note: the DMACIntErrStat Register
contains the same information after masking.) A 1 bit indicates that the error interrupt
request is active prior to masking. Table 551
shows the bit assignments of register of the
DMACRawIntErrStat Register.
Table 548. DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)
Bit Name Function
7:0 IntErrStat Interrupt error status for DMA channels. Each bit represents one channel:
0 - the corresponding channel has no active error interrupt request.
1 - the corresponding channel does have an active error interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 549. DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)
Bit Name Function
7:0 IntErrClr Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit
represents one channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel error interrupt.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 550. DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014)
Bit Name Function
7:0 RawIntTCStat Status of the terminal count interrupt for DMA channels prior to masking. Each bit
represents one channel:
0 - the corresponding channel has no active terminal count interrupt request.
1 - the corresponding channel does have an active terminal count interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
To Next Page
Loading...
