UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 219 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
Once data has been received or sent, the endpoint buffer can be read or written. How this
is accomplished depends on the endpoint’s type and operating mode. The two operating
modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface. See Section 11.14 “
Slave mode operation” for a detailed description of
this mode.
In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See
Section 11.15 “
DMA operation” for a detailed description of this mode.
11.8 Pin description
11.9 Clocking and power management
This section describes the clocking and power management features of the USB Device
Controller.
11.9.1 Power requirements
The USB protocol insists on power management by the device. This becomes very critical
if the device draws power from the bus (bus-powered device). The following constraints
should be met by a bus-powered device:
1. A device in the non-configured state should draw a maximum of 100 mA from the bus.
2. A configured device can draw only up to what is specified in the Max Power field of
the configuration descriptor. The maximum value is 500 mA.
3. A suspended device can draw a maximum of 2.5 mA.
11.9.2 Clocks
The USB device controller clocks are shown in Table 187
Table 186. USB external interface
Name Direction Description
V
BUS
IV
BUS
status input. When this function is not enabled
via its corresponding PINSEL register, it is driven
HIGH internally.
USB_CONNECT O SoftConnect control signal.
USB_UP_LED O GoodLink LED control signal.
USB_D+ I/O Positive differential data.
USB_D- I/O Negative differential data.
To Next Page
Loading...
