UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 520 of 841
NXP Semiconductors
UM10360
Chapter 24: LPC176x/5x Pulse Width Modulator (PWM)
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
24.6.6 PWM Control Register (PWM1PCR - 0x4001 804C)
The PWM Control Register is used to enable and select the type of each PWM channel.
The function of each of the bits are shown in Table 451
.
Table 450: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description
Bit Symbol Value Description Reset
Value
0 Capture on
CAPn.0 rising
edge
0 This feature is disabled. 0
1 A synchronously sampled rising edge on the CAPn.0 input will cause CR0 to be
loaded with the contents of the TC.
1 Capture on
CAPn.0 falling
edge
0 This feature is disabled. 0
1 A synchronously sampled falling edge on CAPn.0 will cause CR0 to be loaded with
the contents of TC.
2 Interrupt on
CAPn.0 event
0 This feature is disabled. 0
1 A CR0 load due to a CAPn.0 event will generate an interrupt.
3 Capture on
CAPn.1rising
edge
0 This feature is disabled. 0
1 A synchronously sampled rising edge on the CAPn.1 input will cause CR1 to be
loaded with the contents of the TC.
4 Capture on
CAPn.1falling
edge
0 This feature is disabled. 0
1 A synchronously sampled falling edge on CAPn.1 will cause CR1 to be loaded with
the contents of TC.
5 Interrupt on
CAPn.1 event
0 This feature is disabled. 0
1 A CR1 load due to a CAPn.1 event will generate an interrupt.
31:6 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
Table 451: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description
Bit Symbol Value Description Reset
Value
1:0 Unused Unused, always zero. NA
2 PWMSEL2 1 Selects double edge controlled mode for the PWM2 output. 0
0 Selects single edge controlled mode for PWM2.
3 PWMSEL3 1 Selects double edge controlled mode for the PWM3 output. 0
0 Selects single edge controlled mode for PWM3.
4 PWMSEL4 1 Selects double edge controlled mode for the PWM4 output. 0
0 Selects single edge controlled mode for PWM4.
5 PWMSEL5 1 Selects double edge controlled mode for the PWM5 output. 0
0 Selects single edge controlled mode for PWM5.
6 PWMSEL6 1 Selects double edge controlled mode for the PWM6 output. 0
0 Selects single edge controlled mode for PWM6.
8:7 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
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