NXP Semiconductors LPC1769 - Register Description

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 577 of 841
NXP Semiconductors
UM10360
Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC)
29.5 Register description
The A/D Converter registers are shown in Table 530.
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 530. ADC registers
Generic
Name
Description Access Reset
value
[1]
AD0 Name &
Address
ADCR A/D Control Register. The ADCR register must be written to select the
operating mode before A/D conversion can occur.
R/W 1 AD0CR -
0x4003 4000
ADGDR A/D Global Data Register. This register contains the ADC’s DONE bit and
the result of the most recent A/D conversion.
R/W NA AD0GDR -
0x4003 4004
ADINTEN A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
R/W 0x100 AD0INTEN -
0x4003 400C
ADDR0 A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0.
RO NA AD0DR0 -
0x4003 4010
ADDR1 A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
RO NA AD0DR1 -
0x4003 4014
ADDR2 A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
RO NA AD0DR2 -
0x4003 4018
ADDR3 A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
RO NA AD0DR3 -
0x4003 401C
ADDR4 A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
RO NA AD0DR4 -
0x4003 4020
ADDR5 A/D Channel 5 Data Register. This register contains the result of the most
recent conversion completed on channel 5.
RO NA AD0DR5 -
0x4003 4024
ADDR6 A/D Channel 6 Data Register. This register contains the result of the most
recent conversion completed on channel 6.
RO NA AD0DR6 -
0x4003 4028
ADDR7 A/D Channel 7 Data Register. This register contains the result of the most
recent conversion completed on channel 7.
RO NA AD0DR7 -
0x4003 402C
ADSTAT A/D Status Register. This register contains DONE and OVERRUN flags
for all of the A/D channels, as well as the A/D interrupt/DMA flag.
RO 0 AD0STAT -
0x4003 4030
ADTRM ADC trim register. R/W 0x0000
0F00
AD0TRM -
0x4003 4034