UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 694 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.6.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and
producing a 32-bit result.
34.2.6.1.1 Syntax
MUL{S}
{cond} {Rd,} Rn, Rm ; Multiply
MLA
{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond is an optional condition code, see Section 34.2.3.7 “
Conditional execution”.
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7 “
Conditional execution”.
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
34.2.6.1.2 Operation
The
MUL
instruction multiplies the values from Rn and Rm, and places the least significant
32 bits of the result in Rd.
The
MLA
instruction multiplies the values from Rn and Rm, adds the value from Ra, and
places the least significant 32 bits of the result in Rd.
The
MLS
instruction multiplies the values from Rn and Rm, subtracts the product from the
value from Ra, and places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or
unsigned.
34.2.6.1.3 Restrictions
In these instructions, do not use SP and do not use PC.
If you use the S suffix with the
MUL
instruction:
• Rd, Rn, and Rm must all be in the range
R0
to
R7
• Rd must be the same as Rm
• you must not use the cond suffix.
34.2.6.1.4 Condition flags
If S is specified, the
MUL
instruction:
• updates the N and Z flags according to the result
• does not affect the C and V flags.
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