UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 61 of 841
NXP Semiconductors
UM10360
Chapter 4: LPC176x/5x Clocking and power control
4.8.4 Deep Power-down mode
In Deep Power-down mode, power is shut off to the entire chip with the exception of the
Real-Time Clock, the RESET
pin, the WIC, and the RTC backup registers. Entry to Deep
Power-down mode causes the DPDFLAG bit in PCON to be set, see Table 44
.
To optimize power conservation, the user has the additional option of turning off or
retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn
off power to the on-chip regulator via the V
DD(REG)(3V3)
pins after entering Deep
Power-down mode.Power to the on-chip regulator must be restored before device
operation can be restarted.
Wake-up from Deep Power-down mode will occur when an external reset signal is
applied, or the RTC interrupt is enabled and an RTC interrupt is generated.
4.8.5 Peripheral power control
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings. This is
detailed in the description of the PCONP register.
4.8.6 Register description
The Power Control function uses registers shown in Table 43. More detailed descriptions
follow.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 43. Power Control registers
Name Description Access Reset
value
[1]
Address
PCON Power Control Register. This register contains
control bits that enable some reduced power
operating modes of the LPC176x/5x. See
Table 44
.
R/W 0x00 0x400F C0C0
PCONP Power Control for Peripherals Register. This
register contains control bits that enable and
disable individual peripheral functions, allowing
elimination of power consumption by peripherals
that are not needed.
R/W 0x400F C0C4
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