UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013  29 of 841
NXP Semiconductors
UM10360
Chapter 3: LPC176x/5x System control
3.7 Other system controls and status flags
Some aspects of controlling LPC176x/5x operation that do not fit into peripheral or other 
registers are grouped here.
3.7.1 System Controls and Status register (SCS - 0x400F C1A0)
The SCS register contains several control/status bits related to the main oscillator. Since 
chip operation always begins using the Internal RC Oscillator, and the main oscillator may 
not be used at all in some applications, it will only be started by software request. This is 
accomplished by setting the OSCEN bit in the SCS register, as described in Table 3-13. 
The main oscillator provides a status flag (the OSCSTAT bit in the SCS register) so that 
software can determine when the oscillator is running and stable. At that point, software 
can control switching to the main oscillator as a clock source. Prior to starting the main 
oscillator, a frequency range must be selected by configuring the 
OSCRANGE bit in the SCS register.
 
Table 13. System Controls and Status register (SCS - address 0x400F C1A0) bit description
Bit Symbol Value Description Access Reset 
value
3:0 - - Reserved. User software should not write ones to 
reserved bits. The value read from a reserved bit is 
not defined.
-NA
4 OSCRANGE Main oscillator range select. R/W 0
0 The frequency range of the main oscillator is 1 MHz 
to 20 MHz.
1 The frequency range of the main oscillator is 
15 MHz to 25 MHz.
5 OSCEN Main oscillator enable. R/W 0
0 The main oscillator is disabled.
1 The main oscillator is enabled, and will start up if 
the correct external circuitry is connected to the 
XTAL1 and XTAL2 pins.
6 OSCSTAT Main oscillator status. RO 0
0 The main oscillator is not ready to be used as a 
clock source.
1 The main oscillator is ready to be used as a clock 
source. The main oscillator must be enabled via the 
OSCEN bit.
31:7 - - Reserved. User software should not write ones to 
reserved bits. The value read from a reserved bit is 
not defined.
-NA