NXP Semiconductors LPC1769 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 44 of 841
NXP Semiconductors
UM10360
Chapter 4: LPC176x/5x Clocking and power control
4.5.12 Examples of PLL0 settings
The following table gives a summary of examples that illustrate selecting PLL0 values
based on different system requirements.
Example 1
Assumptions:
• The USB interface will not be used in the application, or will be clocked by PLL1.
• The desired CPU rate is 100 MHz.
• An external 10 MHz crystal or clock source will be used as the system clock source.
Calculations:
M = (F
CCO
 N) / (2  F
IN
)
A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M),
both result in better PLL operational stability and lower output jitter. Lower values of F
CCO
also save power. So, the process of determining PLL setup parameters involves looking
for the smallest N and M values giving the lowest F
CCO
value that will support the required
CPU and/or USB clocks. It is usually easier to work backward from the desired output
clock rate and determine a target F
CCO
rate, then find a way to obtain that F
CCO
rate from
the available input clock.
Potential precise values of F
CCO
are integer multiples of the desired CPU clock. In this
example, it is clear that the smallest frequency for F
CCO
that can produce the desired CPU
clock rate and is within the PLL0 operating range of 275 to 550 MHz is 300 MHz
(3  100 MHz).
Assuming that the PLL pre-divide is 1 (N = 1), the equation above gives
M = ((300  10
6
 1) / (2  10  10
6
) = 300 / 20 = 15. Since the result is an integer, there is
no need to look any further for a good set of PLL0 configuration values. The value written
to PLL0CFG would be 0x0E (N - 1 = 0; M - 1 = 14 gives 0x0E).
The PLL output must be further divided in order to produce the CPU clock. This is
accomplished using a separate divider that is described later in this chapter, see
Section 4.7.1
.
Table 27. Summary of PLL0 examples
Example Description
1 • The PLL0 clock source is 10 MHz.
• PLL0 is not used as the USB clock source, or the USB interface is not used.
• The desired CPU clock is 100 MHz.
2 • The PLL0 clock source is 4 MHz.
• PLL0 is used as the USB clock source.
• The desired CPU clock is 60 MHz.
3 • The PLL0 clock source is the 32.768 kHz RTC clock.
• PLL0 is not used as the USB clock source, or the USB interface is not used.
• The desired CPU clock is 72 MHz.

NXP Semiconductors LPC1769 Specifications

General

Brand	NXP Semiconductors
Model	LPC1769
Category	Microcontrollers
Language	English