UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 319 of 841
15.1 Basic configuration
The UART1 peripheral is configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bits PCUART1.
Remark: On reset, UART1 is enabled (PCUART1 = 1).
2. Peripheral clock: In the PCLKSEL0 register (Table 40
), select PCLK_UART1.
3. Baud rate: In register U1LCR (Table 298
), set bit DLAB =1. This enables access to
registers DLL (Table 292
) and DLM (Table 293) for setting the baud rate. Also, if
needed, set the fractional baud rate in the fractional divider register (Table 305
).
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0FCR (Table 297
) to enable
FIFO.
5. Pins: Select UART pins through PINSEL registers and pin modes through the
PINMODE registers (Section 8.5
).
Remark: UART receive pins should not have pull-down resistors enabled.
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U1LCR (Table 298
).
This enables access to U1IER (Table 294
). Interrupts are enabled in the NVIC using
the appropriate Interrupt Set Enable register.
7. DMA: UART1 transmit and receive functions can operated with the GPDMA controller
(see Table 543
).
15.2 Features
• Full modem control handshaking available
• Data sizes of 5, 6, 7, and 8 bits.
• Parity generation and checking: odd, even mark, space or none.
• One or two stop bits.
• 16 byte Receive and Transmit FIFOs.
• Built-in baud rate generator, including a fractional rate divider for great versatility.
• Supports DMA for both transmit and receive.
• Auto-baud capability
• Break generation and detection.
• Multiprocessor addressing mode.
• RS-485 support.
UM10360
Chapter 15: LPC176x/5x UART1
Rev. 3 — 19 December 2013 User manual
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