UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 750 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
• Section 34.4.3.9 “System Handler Priority Registers”
• Section 34.4.2.7 “Interrupt Priority Registers”.
Remark: Configurable priority values are in the range 0 to 31. This means that the Reset,
Hard fault, and NMI exceptions, with fixed negative priority values, always have higher
priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to
IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are
asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the
lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are
pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is
preempted if a higher priority exception occurs. If an exception occurs with the same
priority as the exception being handled, the handler is not preempted, irrespective of the
exception number. However, the status of the new interrupt changes to pending.
34.3.3.6 Interrupt priority grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping.
This divides each interrupt priority register entry into two fields:
Only the group priority determines preemption of interrupt exceptions. When the
processor is executing an interrupt exception handler, another interrupt with the same
group priority as the interrupt being handled does not preempt the handler,
• an upper field that defines the group priority
• a lower field that defines a subpriority within the group.
If multiple pending interrupts have the same group priority, the subpriority field determines
the order in which they are processed. If multiple pending interrupts have the same group
priority and subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority,
see Section 34.4.3.6 “
Application Interrupt and Reset Control Register”.
34.3.3.7 Exception entry and return
Descriptions of exception handling use the following terms:
• Preemption
When the processor is executing an exception handler, an exception can preempt the
exception handler if its priority is higher than the priority of the exception being
handled. See Section 34.3.3.6
for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions.
See Section 34.3.3.7.1
more information.
• Return
This occurs when the exception handler is completed, and:
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