NXP Semiconductors LPC1769 - Error Conditions

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User manual Rev. 3 — 19 December 2013 591 of 841
NXP Semiconductors
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Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.4.1.6.3 Error conditions
An error during a DMA transfer is flagged directly by the peripheral by asserting an Error
response on the AHB bus during the transfer. The DMA Controller automatically disables
the DMA stream after the current transfer has completed, and can optionally generate an
error interrupt to the CPU. This error interrupt can be masked.
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Table 542. Endian behavior
…continued
Source
endian
Destination
endian
Source
width
Destination
width
Source
transfer
no/byte lane
Source data Destination
transfer
no/byte lane
Destination data