NXP Semiconductors LPC1769 - CONTROL Register; Exceptions and Interrupts

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User manual Rev. 3 — 20 December 2013 735 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
[1] This field is similar to the priority fields in the interrupt priority registers. The processor implements only
bits[7:M] of this field, bits[M-1:0] read as zero and ignore writes. The value of M depends on the specific
device. See Section 34.4.2.7 “
Interrupt Priority Registers” for more information. Remember that higher
priority field values correspond to lower exception priorities.
34.3.1.3.7 CONTROL register
The CONTROL register controls the stack used and the privilege level for software
execution when the processor is in Thread mode. See the register summary in Table 626
for its attributes. The bit assignments are shown in Table 634
.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active
stack pointer bit of the CONTROL register when in Handler mode. The exception entry
and return mechanisms update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the
process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode
to the PSP, use the
MSR instruction to set the Active stack pointer bit to 1, see
Section 34.2.10.7 “
MSR”.
Remark: When changing the stack pointer, software must use an
ISB instruction
immediately after the
MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer. See Section 34.2.10.5 “
ISB”
34.3.1.4 Exceptions and interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and
the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An
exception changes the normal flow of software control. The processor uses handler mode
to handle all exceptions except for reset. See Section 34.3.3.7.1
and Section 34.3.3.7.2
for more information.
Table 633. BASEPRI register bit assignments
Bits Name Function
[31:8] - Reserved
[7:0] BASEPRI
[1]
Priority mask bits:
0x0000 = no effect
Nonzero = defines the base priority for exception processing.
The processor does not process any exception with a priority value
greater than or equal to BASEPRI.
Table 634. CONTROL register bit assignments
Bits Name Function
[31:2] - Reserved
[1] Active stack
pointer
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
[0] Thread mode
privilege level
Defines the Thread mode privilege level:
0 = privileged
1 = unprivileged.