UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 364 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
Note that a content change of the Error Warning Limit Register is possible only if the
Reset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.
16.7.8 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR -
0x4004 801C)
This read-only register contains three status bytes in which the bits not related to
transmission are identical to the corresponding bits in the Global Status Register, while
those relating to transmission reflect the status of each of the 3 Tx Buffers.
Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit
description
Bit Symbol Value Function Reset
Value
RM
Set
0 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0
1 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0
2 TBS1
[1]
Transmit Buffer Status 1. 1 1
0(locked) Software cannot access the Tx Buffer 1 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
1(released) Software may write a message into the Transmit Buffer 1 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
3TCS1
[2]
Transmission Complete Status. 1 x
0(incomplete) The previously requested transmission for Tx Buffer 1 is not complete.
1(complete) The previously requested transmission for Tx Buffer 1 has been successfully
completed.
4 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0
5 TS1 Transmit Status 1. 1 0
0(idle) There is no transmission from Tx Buffer 1.
1(transmit) The CAN Controller is transmitting a message from Tx Buffer 1.
6 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0
7 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0
8 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0
9 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0
10 TBS2
[1]
Transmit Buffer Status 2. 1 1
0(locked) Software cannot access the Tx Buffer 2 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
1(released) Software may write a message into the Transmit Buffer 2 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
11 TCS2
[2]
Transmission Complete Status. 1 x
0(incomplete) The previously requested transmission for Tx Buffer 2 is not complete.
1(complete) The previously requested transmission for Tx Buffer 2 has been successfully
completed.
12 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0
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