UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 658 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register
to trap all unaligned accesses, see Section 34.4.3.8 “
Configuration and Control Register”.
34.2.3.6 PC-relative expressions
A PC-relative expression or label is a symbol that represents the address of an instruction
or literal data. It is represented in the instruction as the PC value plus or minus a numeric
offset. The assembler calculates the required offset from the label and the address of the
current instruction. If the offset is too big, the assembler produces an error.
Note
• For
B
,
BL
,
CBNZ
, and
CBZ
instructions, the value of the PC is the address of the current
instruction plus 4 bytes.
• For all other instructions that use labels, the value of the PC is the address of the
current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it
word-aligned.
• Your assembler might permit other syntaxes for PC-relative expressions, such as a
label plus or minus a number, or an expression of the form
[PC, #number]
.
34.2.3.7 Conditional execution
Most data processing instructions can optionally update the condition flags in the
Application Program Status Register (APSR) according to the result of the operation,
see Section 34.3.1.3.5 “
Program Status Register”. Some instructions update all flags, and
some only update a subset. If a flag is not updated, the original value is preserved. See
the instruction descriptions for the flags they affect.
You can execute an instruction conditionally, based on the condition flags set in another
instruction, either:
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition
code suffixes to instructions. See Table 615
for a list of the suffixes to add to instructions
to make them conditional instructions. The condition code suffix enables the processor to
test a condition based on the flags. If the condition test of a conditional instruction fails,
the instruction:
• does not execute
• does not write any value to its destination register
• does not affect any of the flags
• does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then
instruction block. See Section 34.2.9.3
for more information and restrictions when using
the
IT
instruction. Depending on the vendor, the assembler might automatically insert an
IT
instruction if you have conditional instructions outside the IT block.
Use the
CBZ
and
CBNZ
instructions to compare the value of a register against zero and
branch on the result.
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