UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 365 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
[1] If the CPU tries to write to this Transmit Buffer when the Transmit Buffer Status bit is '0' (locked), the written byte is not accepted and is
lost without this being signalled.
[2] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit
is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully.
16.7.9 CAN Receive Frame Status register (CAN1RFS - 0x4004 4020,
This register defines the characteristics of the current received message. It is read-only in
normal operation but can be written for testing purposes if the RM bit in CANxMOD is 1.
13 TS2 Transmit Status 2. 1 0
0(idle) There is no transmission from Tx Buffer 2.
1(transmit) The CAN Controller is transmitting a message from Tx Buffer 2.
14 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0
15 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0
16 RBS Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR. 0 0
17 DOS Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR. 0 0
18 TBS3
[1]
Transmit Buffer Status 3. 1 1
0(locked) Software cannot access the Tx Buffer 3 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
1(released) Software may write a message into the Transmit Buffer 3 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
19 TCS3
[2]
Transmission Complete Status. 1 x
0(incomplete) The previously requested transmission for Tx Buffer 3 is not complete.
1(complete) The previously requested transmission for Tx Buffer 3 has been successfully
completed.
20 RS Receive Status. This bit is identical to the RS bit in the GSR. 1 0
21 TS3 Transmit Status 3. 1 0
0(idle) There is no transmission from Tx Buffer 3.
1(transmit) The CAN Controller is transmitting a message from Tx Buffer 3.
22 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0
23 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0
31:24 - Reserved, the value read from a reserved bit is not defined. NA
Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit
description …continued
Bit Symbol Value Function Reset
Value
RM
Set
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