NXP Semiconductors LPC1769 - Interrupt Priority Register 3 (IPR3 - 0 Xe000 E40 C); Interrupt Priority Register 4 (IPR4 - 0 Xe000 E410); Interrupt Priority Register 5 (IPR5 - 0 Xe000 E414)

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User manual Rev. 3 — 19 December 2013 89 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C)
The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
6.5.15 Interrupt Priority Register 4 (IPR4 - 0xE000 E410)
The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
6.5.16 Interrupt Priority Register 5 (IPR5 - 0xE000 E414)
The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000 E40C)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_I2C2 I
2
C2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_SPI SPI Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_SSP0 SSP0 Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_SSP1 SSP1 Interrupt Priority. See functional description for bits 7-3.
Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000 E410)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_PLL0 PLL0 (Main PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_RTC Real Time Clock (RTC) Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_EINT0 External Interrupt 0 Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_EINT1 External Interrupt 1 Interrupt Priority. See functional description for bits 7-3.
Table 67. Interrupt Priority Register 5 (IPR5 - 0xE000 E414)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_EINT2 External Interrupt 2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_EINT3 External Interrupt 3 Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_ADC ADC Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_BOD BOD Interrupt Priority. See functional description for bits 7-3.