UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 279 of 841
NXP Semiconductors
UM10360
Chapter 13: LPC176x/5x USB OTG
13.8.2 OTG Interrupt Status Register (OTGIntSt - 0x5000 C100)
Bits in this register are set by hardware when the interrupt event occurs during the HNP
handoff sequence. See Section 13.9
for more information on when these bits are set.
13.8.3 OTG Interrupt Enable Register (OTGIntEn - 0x5000 C104)
Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate
an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT
interrupt line in the USBIntSt register.
The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.
3 USB_HOST_INT USB host interrupt line status. This bit is read-only. 0
4 USB_ATX_INT External ATX interrupt line status. This bit is read-only. 0
5 USB_OTG_INT OTG interrupt line status. This bit is read-only. 0
6 USB_I2C_INT I
2
C module interrupt line status. This bit is read-only. 0
7 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
8 USB_NEED_CLK USB need clock indicator. This bit is read-only. 1
30:9 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the
NVIC does not see the ORed output of the USB interrupt
lines.
1
Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit
description …continued
Bit Symbol Description Reset
Value
Table 258. OTG Interrupt Status register (OTGIntSt - address 0x5000 C100) bit description
Bit Symbol Description Reset
Value
0 TMR Timer time-out. 0
1 REMOVE_PU Remove pull-up.
This bit is set by hardware to indicate that software
needs to disable the D+ pull-up resistor.
0
2 HNP_FAILURE HNP failed.
This bit is set by hardware to indicate that the HNP
switching has failed.
0
3 HNP_SUCCESS HNP succeeded.
This bit is set by hardware to indicate that the HNP
switching has succeeded.
0
31:4 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
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