UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 518 of 841
NXP Semiconductors
UM10360
Chapter 24: LPC176x/5x Pulse Width Modulator (PWM)
24.6.4 PWM Match Control Register (PWM1MCR - 0x4001 8014)
The PWM Match Control Registers are used to control what operations are performed
when one of the PWM Match Registers matches the PWM Timer Counter. The function of
each of the bits is shown in Table 449
.
Table 448. PWM Count control Register (PWM1CTCR - address 0x4001 8070) bit description
Bit Symbol Value Description Reset
Value
1:0 Counter/
Timer Mode
00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale
Register.
00
01 Counter Mode: the TC is incremented on rising edges of the PCAP input selected by
bits 3:2.
10 Counter Mode: the TC is incremented on falling edges of the PCAP input selected by
bits 3:2.
11 Counter Mode: the TC is incremented on both edges of the PCAP input selected by
bits 3:2.
3:2 Count Input
Select
When bits 1:0 of this register are not 00, these bits select which PCAP pin which
carries the signal used to increment the TC.
00
00 PCAP1.0
01 PCAP1.1 (Other combinations are reserved)
31:4 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description
Bit Symbol Value Description Reset
Value
0 PWMMR0I 1 Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in
the PWMTC.
0
0 This interrupt is disabled.
1 PWMMR0R 1 Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it. 0
0 This feature is disabled.
2 PWMMR0S 1 Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR0 matches the PWMTC.
0
0 This feature is disabled
3 PWMMR1I 1 Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in
the PWMTC.
0
0 This interrupt is disabled.
4 PWMMR1R 1 Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it. 0
0 This feature is disabled.
5 PWMMR1S 1 Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR1 matches the PWMTC.
0
0 This feature is disabled.
6 PWMMR2I 1 Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in
the PWMTC.
0
0 This interrupt is disabled.
7 PWMMR2R 1 Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it. 0
0 This feature is disabled.
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