UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 402 of 841
17.1 Basic configuration
The SPI is configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bit PCSPI.
Remark: On reset, the SPI is enabled (PCSPI = 1).
2. Clock: In the PCLKSEL0 register (Table 40
), set bit PCLK_SPI. In master mode, the
clock must be an even number greater than or equal to 8 (see Section 17.7.4
).
3. Pins: The SPI pins are configured using both PINSEL0 (Table 79
) and PINSEL1
(Table 80
), as well as the PINMODE (Section 8.4) register. PINSEL0[31:30] is used to
configure the SPI CLK pin. PINSEL1[1:0], PINSEL1[3:2] and PINSEL1[5:4] are used
to configure the pins SSEL, MISO and MOSI, respectively.
4. Interrupts: The SPI interrupt flag is enabled using the S0SPINT[0] bit (Section 17.7.7
).
The SPI interrupt flag must be enabled in the NVIC, see Table 50
.
Remark: SSP0 is intended to be used as an alternative for the SPI interface. SPI is
included as a legacy peripheral.
17.2 Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex Communication.
• SPI master or slave.
• Maximum data bit rate of one eighth of the peripheral clock rate.
• 8 to 16 bits per transfer.
17.3 SPI overview
SPI is a full duplex serial interface. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.
UM10360
Chapter 17: LPC176x/5x SPI
Rev. 3 — 19 December 2013 User manual
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