UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 257 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
11.15.3 Triggering the DMA engine
An endpoint raises a DMA request when Slave mode is disabled by setting the
corresponding bit in the USBEpIntEn register to 0 (Section 11.10.3.2
) and an endpoint
interrupt occurs (see Section 11.10.7.1 “
USB DMA Request Status register (USBDMARSt
- 0x5000 C250)”).
A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in
USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found for
the endpoint.
All endpoints share a single DMA channel to minimize hardware overhead. If more than
one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint
number is processed first.
In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command
(Section 11.12.3
).
11.15.4 The DMA descriptor
DMA transfers are described by a data structure called the DMA Descriptor (DD).
DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at
word-aligned addresses.
DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints
are five words long.
The parameters associated with a DMA transfer are:
• The start address of the DMA buffer
• The length of the DMA buffer
• The start address of the next DMA descriptor
• Control information
• Count information (number of bytes transferred)
• Status information
Table 251
lists the DMA descriptor fields.
Table 251. DMA descriptor
Word
position
Access
(H/W)
Access
(S/W)
Bit
position
Description
0 R R/W 31:0 Next_DD_pointer
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