UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 570 of 841
28.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate Watchdog reset.
• Programmable 32-bit timer with internal pre-scaler.
• Selectable time period from (T
WDCLK
256 4) to (T
WDCLK
2
32
4) in multiples of
T
WDCLK
4.
• The Watchdog clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the APB peripheral clock (PCLK, see Table 40
), or the RTC oscillator. This
gives a wide range of potential timing choices for Watchdog operation under different
power reduction conditions. For increased reliability, it also provides the ability to run
the Watchdog timer from an entirely internal source that is not dependent on an
external crystal and its associated components and wiring.
• The Watchdog timer can be configured to run in Deep Sleep mode when using the
IRC as the clock source.
28.2 Applications
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
For interaction of the on-chip watchdog and other peripherals, especially the reset and
boot-up procedures, please read Section 3.4 “
Reset” on page 19 of this document.
UM10360
Chapter 28: LPC176x/5x Watchdog Timer (WDT)
Rev. 3 — 19 December 2013 User manual
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