UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 680 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
– Rn must also be SP
– any shift in Operand2 must be limited to a maximum of 3 bits using
LSL
• Rn can be SP only in
ADD
and
SUB
• Rd can be PC only in the cond instruction where:
– you must not specify the S suffix
– Rm must not be PC and must not be SP
– if the instruction is conditional, it must be the last instruction in the IT block
• with the exception of the cond instruction, Rn can be PC only in
ADD
and
SUB
, and only
with the additional restrictions:
– you must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
Note
• When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to
b00 before performing the calculation, making the base address for the calculation
word-aligned.
• If you want to generate the address of an instruction, you have to adjust the constant
based on the value of the PC. ARM recommends that you use the
ADR
instruction
instead of
ADD
or
SUB
with Rn equal to the PC, because your assembler automatically
calculates the correct constant for the
ADR
instruction.
When Rd is PC in the cond instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
34.2.5.1.4 Condition flags
If S is specified, these instructions update the N, Z, C and V flags according to the result.
34.2.5.1.5 Examples
ADD R2, R1, R3
SUBS R8, R6, #240 ; Sets the flags on the result
RSB R4, R4, #1280 ; Subtracts contents of R4 from 1280
ADCHI R11, R0, R3 ; Only executed if C flag set and Z
; flag clear
34.2.5.1.6 Multiword arithmetic examples
Section
shows two instructions that add a 64-bit integer contained in R2 and R3 to
another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.
Multiword values do not have to use consecutive registers. Section
shows instructions
that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6,
R2, and R8. The example stores the result in R6, R9, and R2.
64-bit addition:
ADDS R4, R0, R2 ; add the least significant words
ADC R5, R1, R3 ; add the most significant words with carry
To Next Page
Loading...
