UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 781 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
Remark: The UFSR bits are sticky. This means as one or more fault occurs, the
associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit,
or by a reset.
Table 670. UFSR bit assignments
Bits Name Function
[15:10] - Reserved.
[9] DIVBYZERO Divide by zero usage fault:
0 = no divide by zero fault, or divide by zero trapping not enabled
1 = the processor has executed an
SDIV
or
UDIV
instruction with a divisor
of 0.
When the processor sets this bit to 1, the PC value stacked for the
exception return points to the instruction that performed the divide by
zero.
Enable trapping of divide by zero by setting the DIV_0_TRP bit in the
CCR to 1, see Table 662
.
[8] UNALIGNED Unaligned access usage fault:
0 = no unaligned access fault, or unaligned access trapping not enabled
1 = the processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP
bit in the CCR to 1, see Table 662
.
Unaligned
LDM
,
STM
,
LDRD
, and
STRD
instructions always fault irrespective
of the setting of UNALIGN_TRP.
[7:4] - Reserved.
[3] NOCP No coprocessor usage fault. The processor does not support
coprocessor instructions:
0 = no usage fault caused by attempting to access a coprocessor
1 = the processor has attempted to access a coprocessor.
[2] INVPC Invalid PC load usage fault, caused by an invalid PC load by
EXC_RETURN:
0 = no invalid PC load usage fault
1 = the processor has attempted an illegal load of EXC_RETURN to the
PC, as a result of an invalid context, or an invalid EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return
points to the instruction that tried to perform the illegal load of the PC.
[1] INVSTATE Invalid state usage fault:
0 = no invalid state usage fault
1 = the processor has attempted to execute an instruction that makes
illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return
points to the instruction that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
[0] UNDEFINSTR Undefined instruction usage fault:
0 = no undefined instruction usage fault
1 = the processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return
points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
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