UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 284 of 841
NXP Semiconductors
UM10360
Chapter 13: LPC176x/5x USB OTG
2 NAI No Acknowledge Interrupt. After every byte of data is sent, the
transmitter expects an acknowledge from the receiver. This bit is
set if the acknowledge is not received. It is cleared when a byte
is written to the master TX FIFO.
0
0 Last transmission received an acknowledge.
1 Last transmission did not receive an acknowledge.
3 DRMI Master Data Request Interrupt. Once a transmission is started,
the transmitter must have data to transmit as long as it isn’t
followed by a stop condition or it will hold SCL low until more
data is available. The Master Data Request bit is set when the
master transmitter is data-starved. If the master TX FIFO is
empty and the last byte did not have a STOP condition flag, then
SCL is held low until the CPU writes another byte to transmit.
This bit is cleared when a byte is written to the master TX FIFO.
0
0 Master transmitter does not need data.
1 Master transmitter needs data.
4 DRSI Slave Data Request Interrupt. Once a transmission is started,
the transmitter must have data to transmit as long as it isn’t
followed by a STOP condition or it will hold SCL low until more
data is available. The Slave Data Request bit is set when the
slave transmitter is data-starved. If the slave TX FIFO is empty
and the last byte transmitted was acknowledged, then SCL is
held low until the CPU writes another byte to transmit. This bit is
cleared when a byte is written to the slave Tx FIFO.
0
0 Slave transmitter does not need data.
1 Slave transmitter needs data.
5 Active Indicates whether the bus is busy. This bit is set when a START
condition has been seen. It is cleared when a STOP condition is
seen..
0
6 SCL The current value of the SCL signal. -
7 SDA The current value of the SDA signal. -
8 RFF Receive FIFO Full (RFF). This bit is set when the RX FIFO is full
and cannot accept any more data. It is cleared when the RX
FIFO is not full. If a byte arrives when the Receive FIFO is full,
the SCL is held low until the CPU reads the RX FIFO and makes
room for it.
0
0 RX FIFO is not full
1 RX FIFO is full
9 RFE Receive FIFO Empty. RFE is set when the RX FIFO is empty
and is cleared when the RX FIFO contains valid data.
1
0 RX FIFO contains data.
1 RX FIFO is empty
10 TFF Transmit FIFO Full. TFF is set when the TX FIFO is full and is
cleared when the TX FIFO is not full.
0
0 TX FIFO is not full.
1 TX FIFO is full
Table 265. I
2
C status register (I2C_STS - address 0x5000 C304) bit description …continued
Bit Symbol Value Description Reset
Value
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