UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 308 of 841
NXP Semiconductors
UM10360
Chapter 14: LPC176x/5x UART0/2/3
Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)
bit description
Bit Symbol Value Description Reset
Value
0 Receiver Data
Ready (RDR)
UnLSR0 is set when the UnRBR holds an unread character and is cleared when
the UARTn RBR FIFO is empty.
0
0 The UARTn receiver FIFO is empty.
1 The UARTn receiver FIFO is not empty.
1 Overrun Error
(OE)
The overrun error condition is set as soon as it occurs. An UnLSR read clears
UnLSR1. UnLSR1 is set when UARTn RSR has a new character assembled and
the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be
overwritten and the character in the UARTn RSR will be lost.
0
0 Overrun error status is inactive.
1 Overrun error status is active.
2 Parity Error (PE) When the parity bit of a received character is in the wrong state, a parity error
occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is
dependent on UnFCR[0].
Note: A parity error is associated with the character at the top of the UARTn RBR
FIFO.
0
0 Parity error status is inactive.
1 Parity error status is active.
3 Framing Error
(FE)
When the stop bit of a received character is a logic 0, a framing error occurs. An
UnLSR read clears UnLSR[3]. The time of the framing error detection is
dependent on UnFCR0. Upon detection of a framing error, the Rx will attempt to
resynchronize to the data and assume that the bad stop bit is actually an early
start bit. However, it cannot be assumed that the next received byte will be correct
even if there is no Framing Error.
Note: A framing error is associated with the character at the top of the UARTn
RBR FIFO.
0
0 Framing error status is inactive.
1 Framing error status is active.
4 Break Interrupt
(BI)
When RXDn is held in the spacing state (all zeroes) for one full character
transmission (start, data, parity, stop), a break interrupt occurs. Once the break
condition has been detected, the receiver goes idle until RXDn goes to marking
state (all ones). An UnLSR read clears this status bit. The time of break detection
is dependent on UnFCR[0].
Note: The break interrupt is associated with the character at the top of the UARTn
RBR FIFO.
0
0 Break interrupt status is inactive.
1 Break interrupt status is active.
5 Transmitter
Holding Register
Empty (THRE))
THRE is set immediately upon detection of an empty UARTn THR and is cleared
on a UnTHR write.
1
0 UnTHR contains valid data.
1 UnTHR is empty.
6 Transmitter
Empty (TEMT)
TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when
either the UnTSR or the UnTHR contain valid data.
1
0 UnTHR and/or the UnTSR contains valid data.
1 UnTHR and the UnTSR are empty.
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