NXP Semiconductors LPC1769 - Page 604

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User manual Rev. 3 — 19 December 2013 604 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
Table 563. DMA channel control registers (DMACCxControl - 0x5000 41xC)
Bit Name Function
11:0 TransferSize Transfer size. This field sets the size of the transfer. The transfer size value must be set before the
channel is enabled. Transfer size is updated as data transfers are completed.
A read from this field indicates the number of transfers completed on the destination bus. Reading
the register when the channel is active does not give useful information because by the time that the
software has processed the value read, the channel might have progressed. It is intended to be used
only when a channel is enabled and then disabled.
14:12 SBSize Source burst size. Indicates the number of transfers that make up a source burst. This value must be
set to the burst size of the source peripheral, or if the source is memory, to the memory boundary
size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes
active in the source peripheral.
000 - 1
001 - 4
010 - 8
011 - 16
100 - 32
101 - 64
110 - 128
111 - 256
17:15 DBSize Destination burst size. Indicates the number of transfers that make up a destination burst transfer
request. This value must be set to the burst size of the destination peripheral or, if the destination is
memory, to the memory boundary size. The burst size is the amount of data that is transferred when
the DMACBREQ signal goes active in the destination peripheral.
000 - 1
001 - 4
010 - 8
011 - 16
100 - 32
101 - 64
110 - 128
111 - 256
20:18 SWidth Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and
destination widths can be different from each other. The hardware automatically packs and unpacks
the data as required.
000 - Byte (8-bit)
001 - Halfword (16-bit)
010 - Word (32-bit)
011 to 111 - Reserved
23:21 DWidth Destination transfer width. Transfers wider than the AHB master bus width are not supported. The
source and destination widths can be different from each other. The hardware automatically packs
and unpacks the data as required.
000 - Byte (8-bit)
001 - Halfword (16-bit)
010 - Word (32-bit)
011 to 111 - Reserved
25:24 - Reserved, and must be written as 0.