NXP Semiconductors LPC1769 - Page 650

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User manual Rev. 3 — 20 December 2013 650 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
ISB - Instruction Synchronization Barrier - Section 34.2.10.5
IT - If-Then condition block - Section 34.2.9.3
LDM Rn{!}, reglist Load Multiple registers, increment after - Section 34.2.4.6
LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before - Section 34.2.4.6
LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after - Section 34.2.4.6
LDR Rt, [Rn, #offset] Load Register with word - Section 34.2.4
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte - Section 34.2.4
LDRD Rt, Rt2, [Rn, #offset] Load Register with double word - Section 34.2.4.2
LDREX Rt, [Rn, #offset] Load Register Exclusive - Section 34.2.4.8
LDREXB Rt, [Rn] Load Register Exclusive with byte - Section 34.2.4.8
LDREXH Rt, [Rn] Load Register Exclusive with halfword - Section 34.2.4.8
LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword - Section 34.2.4
LDRSB, LDRSBT Rt, [Rn, #offset] Load Register with signed byte - Section 34.2.4
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword - Section 34.2.4
LDRT Rt, [Rn, #offset] Load Register with word - Section 34.2.4
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C Section 34.2.5.3
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C Section 34.2.5.3
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result - Section 34.2.6.1
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result - Section 34.2.6.1
MOV, MOVS Rd, Op2 Move N,Z,C Section 34.2.5.6
MOVT Rd, #imm16 Move Top - Section 34.2.5.7
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C Section 34.2.5.6
MRS Rd, spec_reg Move from special register to general register - Section 34.2.10.6
MSR spec_reg, Rm Move from general register to special register N,Z,C,V Section 34.2.10.7
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z Section 34.2.6.1
MVN, MVNS Rd, Op2 Move NOT N,Z,C Section 34.2.5.6
NOP - No Operation - Section 34.2.10.8
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C Section 34.2.5.2
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C Section 34.2.5.2
POP reglist Pop registers from stack - Section 34.2.4.7
PUSH reglist Push registers onto stack - Section 34.2.4.7
RBIT Rd, Rn Reverse Bits - Section 34.2.5.8
REV Rd, Rn Reverse byte order in a word - Section 34.2.5.8
REV16 Rd, Rn Reverse byte order in each halfword - Section 34.2.5.8
REVSH Rd, Rn Reverse byte order in bottom halfword and sign
extend
- Section 34.2.5.8
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C Section 34.2.5.3
RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C Section 34.2.5.3
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V Section 34.2.5.1
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V Section 34.2.5.1
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract - Section 34.2.8.2
Table 612. Cortex-M3 instructions …continued
Mnemonic Operands Brief description Flags Page