UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 801 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
Should Be Zero or Preserved (SBZP) — Write as 0, or all 0s for bit fields, by software,
or preserved by writing the same value back that has been previously read from the same
field on the same processor.
Thread-safe — In a multi-tasking environment, thread-safe functions use safeguard
mechanisms when accessing shared resources, to ensure correct operation without the
risk of shared access conflicts.
Thumb instruction — One or two halfwords that specify an operation for a processor to
perform. Thumb instructions must be halfword-aligned.
Unaligned — A data item stored at an address that is not divisible by the number of bytes
that defines the data size is said to be unaligned. For example, a word stored at an
address that is not divisible by four.
Unpredictable (UNP) — You cannot rely on the behavior. Unpredictable behavior must
not represent security holes. Unpredictable behavior must not halt or hang the processor,
or any parts of the system.
Warm reset — Also known as a core reset. Initializes the majority of the processor
excluding the debug controller and debug logic. This type of reset is useful if you are using
the debugging features of a processor.
WA — See Write-allocate.
WB — See Write-back.
Word — A 32-bit data item.
Write — Writes are defined as operations that have the semantics of a store. Writes
include the Thumb instructions
STM
,
STR
,
STRH
,
STRB
, and
PUSH
.
Write-allocate (WA) — In a write-allocate cache, a cache miss on storing data causes a
cache line to be allocated into the cache.
Write-back (WB) — In a write-back cache, data is only written to main memory when it is
forced out of the cache on line replacement following a cache miss. Otherwise, writes by
the processor only update the cache. This is also known as copyback.
Write buffer — A block of high-speed memory, arranged as a FIFO buffer, between the
data cache and main memory, whose purpose is to optimize stores to main memory.
Write-through (WT) — In a write-through cache, data is written to main memory at the
same time as the cache is updated.
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