EasyManuals Logo

ST STM32WL55JC User Manual

ST STM32WL55JC
1454 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #1006 background imageLoading...
Page #1006 background image
Real-time clock (RTC) RM0453
1006/1454 RM0453 Rev 2
In this case, the RTC precision can be measured during 16 seconds with a maximum error
of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration
resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0]
bit is stuck at 0 when CALW16 is set to 1.
CALW8 bit of the RTC_CALR register can be set to 1 to force a 8-second calibration
cycle period.
In this case, the RTC precision can be measured during 8 seconds with a maximum error of
1.907 ppm (0.5 RTCCLK cycles over 8 s). The long term RTC precision is also reduced to
1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.
Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ICSR/INITF = 0,
by using the follow process:
1. Poll the RTC_ICSR/RECALPF (re-calibration pending flag).
2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then
automatically set to 1
3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration
settings take effect.
32.3.15 Timestamp function
Timestamp is enabled by setting the TSE or ITSE bits of RTC_CR register to 1.
When TSE is set:
The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a timestamp event is detected on the RTC_TS pin.
When TAMPTS is set:
The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a tamper event is detected on the TAMP_INx pinx.
When ITSE is set:
The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when an internal timestamp event is detected. The internal timestamp event is generated by
the switch to the V
BAT
supply.
When a timestamp event occurs, due to internal or external event, the timestamp flag bit
(TSF) in RTC_SR register is set. In case the event is internal, the ITSF flag is also set in
RTC_SR register.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp
event occurs.
If a new timestamp event is detected while the timestamp flag (TSF) is already set, the
timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and
RTC_TSDR) maintain the results of the previous event.
Note: TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization
process.
There is no delay in the setting of TSOVF. This means that if two timestamp events are
close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is
recommended to poll TSOVF only after TSF has been set.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32WL55JC and is the answer not in the manual?

ST STM32WL55JC Specifications

General IconGeneral
BrandST
ModelSTM32WL55JC
CategoryMicrocontrollers
LanguageEnglish

Related product manuals