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RM0453 Rev 2 1169/1454

RM0453 Universal synchronous/asynchronous receiver transmitter (USART/UART)

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35.8 USART registers

Refer to Section 1.2 on page 58 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32 bits).

35.8.1 USART control register 1 [alternate] (USART_CR1)

Address offset: 0x00

Reset value: 0x0000 0000

The same register can be used in FIFO mode enabled (this section) and FIFO mode

disabled (next section).

FIFO mode enabled

2. RXFF flag is asserted if the USART receives n+1 data (n being the RXFIFO size): n data in the RXFIFO and 1 data in

USART_RDR. In Stop mode, USART_RDR is not clocked. As a result, this register is not written and once n data are

received and written in the RXFIFO, the RXFF interrupt is asserted (RXFF flag is not set).

3. When OVRDIS = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RXF

FIE

TXFEIE

FIFO

M1 EOBIE RTOIE DEAT[4:0] DEDT[4:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OVER8 CMIE MME M0 WAKE PCE PS PEIE TXFNFIE TCIE RXFNEIE IDLEIE TE RE UESM UE

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 RXFFIE: RXFIFO Full interrupt enable

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated when RXFF = 1 in the USART_ISR register

Bit 30 TXFEIE: TXFIFO empty interrupt enable

This bit is set and cleared by software.

0: Interrupt inhibited

1: USART interrupt generated when TXFE = 1 in the USART_ISR register

Bit 29 FIFOEN: FIFO mode enable

This bit is set and cleared by software.

0: FIFO mode is disabled.

1: FIFO mode is enabled.

This bitfield can only be written when the USART is disabled (UE = 0).

Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode

and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.

ST STM32WL55JC User Manual

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