Low-power timer (LPTIM) RM0453
956/1454 RM0453 Rev 2
28.4.13 Timer enable
The ENABLE bit located in the LPTIM_CR register is used to enable/disable the LPTIM
kernel logic. After setting the ENABLE bit, a delay of two counter clock is needed before the
LPTIM is actually enabled.
The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is
disabled.
28.4.14 Timer counter reset
In order to reset the content of LPTIM_CNT register to zero, two reset mechanisms are
implemented:
• The synchronous reset mechanism: the synchronous reset is controlled by the
COUNTRST bit in the LPTIM_CR register. After setting the COUNTRST bitfield to '1',
the reset signal is propagated in the LPTIM kernel clock domain. So it is important to
note that a few clock pulses of the LPTIM kernel logic elapse before the reset is taken
into account. This makes the LPTIM counter count few extra pluses between the time
when the reset is trigger and it become effective. Since the COUNTRST bit is located in
the APB clock domain and the LPTIM counter is located in the LPTIM kernel clock
domain, a delay of 3 clock cycles of the kernel clock is needed to synchronize the reset
signal issued by the APB clock domain when writing '1' to the COUNTRST bit.
• The asynchronous reset mechanism: the asynchronous reset is controlled by the
RSTARE bit located in the LPTIM_CR register. When this bit is set to '1', any read
access to the LPTIM_CNT register resets its content to zero. Asynchronous reset
should be triggered within a timeframe in which no LPTIM core clock is provided. For
example when LPTIM Input1 is used as external clock source, the asynchronous reset
should be applied only when there is enough insurance that no toggle occurs on the
LPTIM Input1.
It should be noted that to read reliably the content of the LPTIM_CNT register two
successive read accesses must be performed and compared. A read access can be
considered reliable when the value of the two read accesses is equal. Unfortunately
when asynchronous reset is enabled there is no possibility to read twice the
LPTIM_CNT register.
Warning: There is no mechanism inside the LPTIM that prevents the
two reset mechanisms from being used simultaneously. So
developer should make sure that these two mechanisms are
used exclusively.
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